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PX1041A
PCI Express stand-alone X4 PHY
Rev. 01 -- 21 June 2007 Objective data sheet
1. General description
The PX1041A is a high-performance, low-power, four-lane PCI Express electrical PHYsical layer (PHY) that handles the low level PCI Express protocol and signaling. The PX1041A PCI Express PHY is compliant to the PCI Express Base Specification, Rev. 1.0a, and Rev. 1.1. The PX1041A includes features such as Clock and Data Recovery (CDR), data serialization and de-serialization, 8b/10b encoding, analog buffers, elastic buffer and receiver detection, and provides superior performance to the Media Access Control (MAC) layer devices. The PX1041A is a 2.5 Gbit/s PCI Express PHY with 4 x 8-bit data PXPIPE interface. Its PXPIPE interface is a superset of the PHY Interface for the PCI Express (PIPE) specification, enhanced and adapted for off-chip applications with the introduction of a source synchronous clock for transmit and receive data. The 4 x 8-bit data interface operates at 250 MHz with SSTL Class I signaling at 2.5 V or 1.8 V. The SSTL signaling is compatible with the I/O interfaces available in FPGA products. The PX1041A PCI Express PHY supports advanced power management functions. The PX1041AI is for the industrial temperature range (-40 C to +85 C).
2. Features
2.1 PCI Express interface
I I I I I I I I I I I I I Compliant to PCI Express Base Specification 1.0a and 1.1 Four PCI Express 2.5 Gbit/s lane Data and clock recovery from serial stream Serializer and De-serializer (SerDes) Receiver detection 8b/10b coding and decoding, elastic buffer and word alignment Supports direct disparity control for use in transmitting compliance pattern Supports lane polarity inversion Low jitter and Bit Error Rate (BER) Supports PCI Express-side parallel loopback Supports PXPIPE-side parallel loopback Supports receiver lane-to-lane deskew (optional) Supports lane reversal (optional)
2.2 PHY/MAC interface
I Based on Intel PHY Interface for PCI Express architecture v2.0 (PIPE) I Adapted for off-chip with additional synchronous clock signals (PXPIPE)
NXP Semiconductors
PX1041A
PCI Express stand-alone X4 PHY
I PIPE mode selectable I 4 x 8-bit parallel data interface for transmit and receive at 250 MHz I SSTL Class I signaling at 2.5 V or 1.8 V, without select pin
2.3 JTAG interface
I JTAG (IEEE 1149.1) boundary scan interface I Built-In Self Test (BIST) controller tests SerDes and I/O blocks at speed I 3.3 V CMOS signaling
2.4 Power management
I Dissipates < 1 W in L0 normal mode I Support power management of L0, L0s, L1, and L2
2.5 Clock
I 100 MHz external reference clock with 300 ppm tolerance I Supports spread spectrum clock to reduce EMI I On-chip reference clock termination
2.6 Miscellaneous
I LFBGA208 lead free package I Operating ambient temperature N PX1041A for commercial range: 0 C to +70 C N PX1041AI for industrial range: -40 C to +85 C I ESD protection voltage for Human Body Model (HBM): 2000 V
3. Quick reference data
Table 1. VDDD1 VDDD2 VDDD3 VDD VDDA1 VDDA2 fclk(ref) Tamb Quick reference data Conditions for JTAG I/O for SSTL_18 I/O for SSTL_2 I/O digital supply voltage 3 supply voltage analog supply voltage 1 analog supply voltage 2 reference clock frequency ambient temperature operating commercial industrial
[1] No select pin needed.
[1] [1]
Symbol Parameter digital supply voltage 1 digital supply voltage 2
Min 3.0 1.7 2.3 1.15 1.15 1.15 3.0 99.97 0 -40
Typ 3.3 1.8 2.5 1.2 1.2 1.2 3.3 100 -
Max 3.6 1.9 2.7 1.25 1.25 1.25 3.6 100.03 +70 +85
Unit V V V V V V V MHz C C
for core for high-speed serial I/O and PVT for serializer for serializer
PX1041A_1
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Objective data sheet
Rev. 01 -- 21 June 2007
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NXP Semiconductors
PX1041A
PCI Express stand-alone X4 PHY
4. Ordering information
Table 2. Ordering information Solder process Pb-free (SnAgCu solder ball compound) Pb-free (SnAgCu solder ball compound) Package Name PX1041A-EL1/G PX1041AI-EL1/G LFBGA208 LFBGA208 Description Version plastic low profile fine-pitch ball grid array package; SOT631-4 208 balls; body 15 x 15 x 1 mm plastic low profile fine-pitch ball grid array package; SOT631-4 208 balls; body 15 x 15 x 1 mm Type number
5. Marking
Table 3. Line A B C Lead-free package marking Marking PX1041A-EL1/G PX1041AI-EL1/G[1] xxxxxxx 2PGyyww diffusion lot number manufacturing code: 2 = diffusion site P = assembly site G = lead-free yy = year code ww = week code
[1] Industrial temperature range.
Description full basic type number
PX1041A_1
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Objective data sheet
Rev. 01 -- 21 June 2007
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NXP Semiconductors
PX1041A
PCI Express stand-alone X4 PHY
6. Block diagram
L0_RXDATA [7:0]
L0_TXDATA [7:0]
L1_RXDATA[7:0]
L2_RXDATA[7:0]
Ln_TxData0 Ln_TxData1 8b/10b ENCODE PARALLEL TO SERIAL
REGISTER 8 10b/8b DECODE
PCI Express PHY
LANE 0
ELASTIC BUFFER 10 SERIAL TO PARALLEL DATA RECOVERY CIRCUIT CLOCK RECOVERY CIRCUIT PLL K28.5 DETECTION LANE 1 LANE 2 LANE 3
250 MHz clock
TX I/O
RX I/O
bit stream at 2.5 Gbit/s
CLK GENERATOR
REFCLK I/O
L0_TX_P
L0_TX_N
L0_RX_P
REFCLK_P
REFCLK_N
L1_TX_P L1_TX_N
L1_RX_P L1_RX_N
L2_TX_P L2_TX_N
L2_RX_P L2_RX_N
L3_TX_P L3_TX_N
L3_RXDATA[7:0]
002aac432
L1_TXDATA[7:0]
L2_TXDATA[7:0]
L3_TXDATA[7:0]
PCI Express MAC
RESET_N
RXCLK
TXCLK
Fig 1. Block diagram of PX1041A
PX1041A_1
(c) NXP B.V. 2007. All rights reserved.
Objective data sheet
Rev. 01 -- 21 June 2007
L3_RX_P L3_RX_N
L0_RX_N
4 of 36
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PX1041A
PCI Express stand-alone X4 PHY
7. Pinning information
7.1 Pinning
ball A1 index area 1 A B C D E F G H J K L M N P R T U
002aac433
2 3
4 5
6 7
8 9
10 12 14 16 11 13 15 17
PX1041A-EL1/G PX1041AI-EL1/G
Transparent top view
Fig 2. Pin configuration for LFBGA208
PX1041A_1
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Objective data sheet
Rev. 01 -- 21 June 2007
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Objective data sheet Rev. 01 -- 21 June 2007
(c) NXP B.V. 2007. All rights reserved. PX1041A_1
NXP Semiconductors
1 A B C D E F G H J K L M N P R T U REFCLK_P REFCLK_N VSS L0_RX_P L0_RX_N VSS L1_RX_P L1_RX_N VSS L2_RX_P L2_RX_N VSS L3_RX_P L3_RX_N VSS L3_TX_P L3_TX_N
2 TMS TRST_N VDDD1 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
3 TDI TCK TDO PVT VSS L0_TX_P L0_TX_N VSS L1_TX_P L1_TX_N VSS L2_TX_P L2_TX_N VSS L3_ TXDATA0 L3_ TXDATA1 L3_ TXDATA2
4 L0_ RXDATA7 VSS L0_ RXDATAK L0_ RXIDLE VDDA2 VDD VDD VDD VDDA1 VDDA1 VDDA1 VDDA1 VDDA1 L3_ TXCOMP L3_ TXIDLE VSS L3_ TXDATA3
5 L0_ RXDATA5 L0_ RXDATA6
6 L0_ RXDATA4 L0_ RXDATA3
7 L0_ RXDATA2 VSS L0_ RXVALID VDDD2
8 L0_ RXDATA0 L0_ RXDATA1 L0_ RXPOL VDDD2
9 L0_ TXDATA7 L0_ TXDATA6 L0_ TXCOMP VSS
10 L0_ TXDATA5 VSS L0_ TXDATAK VDDD2
11 L0_ TXDATA4 L0_ TXDATA3 L0_ TXIDLE VDDD2
12 L0_ TXDATA2 L0_ TXDATA1 L0_ TXDATA0
13 RESET_N VSS
14 RXCLK PWRDWN1
15 TXCLK DESKEW_ START DESKEW_ VALID PHYSTATUS RXDET_ LOOPB L1_ RXSTATUS2 L1_ RXSTATUS1 L1_ RXSTATUS0 L1_ RXPOL L1_ TXDATAK L1_ TXIDLE L2_ RXIDLE L2_ RXSTATUS2 L2_ RXSTATUS1 L2_ RXSTATUS0 L2_ TXDATA6 L2_ TXDATA5
16 L1_ RXDATA7 VSS L1_ RXDATAK L1_ RXIDLE VSS L1_ RXDATA1 VSS L1_ TXDATA5 L1_ TXDATA3 VSS L1_ TXDATA1 L2_ RXDATAK VSS L2_ RXDATA4 L2_ RXDATA2 VSS L2_ TXDATA7
17 L1_ RXDATA6 L1_ RXDATA5 L1_ RXDATA4 L1_ RXDATA3 L1_ RXDATA2 L1_ RXDATA0 L1_ TXDATA7 L1_ TXDATA6 L1_ TXDATA4 L1_ TXDATA2 L1_ TXDATA0 L2_ RXDATA7 L2_ RXDATA6 L2_ RXDATA5 L2_ RXDATA3
L0_ L0_ RXSTATUS1 RXSTATUS0 L0_ RXSTATUS2 VSS
PIPELOOPB PWRDWN0 VSS LANE REVERSAL L1_ RXVALID VDDD2 VDDD2 VDDD2 VDDD2 L1_ TXCOMP L2_ RXVALID L2_ RXPOL
ENCODING PIPEMODE EN SEL
L3_ RXPOL L3_ TXDATAK L3_ TXDATA4 L3_ TXDATA5
VSS L3_ RXVALID L3_ TXDATA6 L3_ TXDATA7
VDDD3
VDDD3
VSS
VDDD2 L3_ RXDATAK VSS L3_ RXDATA5
VDDD2 L3_ RXIDLE L3_ RXDATA6 L3_ RXDATA7
VDDD2 L2_ TXDATAK L2_ TXDATA1 L2_ TXDATA0
L2_ TXCOMP L2_ TXIDLE VSS L2_ TXDATA2
VSS L2_ TXDATA4 L2_ TXDATA3 VREFS
L3_ L3_ L3_ RXSTATUS0 RXSTATUS1 RXSTATUS2 VSS L3_ RXDATA0 L3_ RXDATA2 L3_ RXDATA1 L3_ RXDATA3 L3_ RXDATA4
PCI Express stand-alone X4 PHY
L2_ RXDATA1 L2_ RXDATA0
002aac434
PX1041A
Transparent top view.
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Fig 3. Ball mapping
NXP Semiconductors
PX1041A
PCI Express stand-alone X4 PHY
7.2 Pin description
The PHY input and output pins are described in Table 4 to Table 11. Note that input and output is defined from the perspective of the PHY. Thus a signal on a pin described as an output is driven by the PHY and a signal on a pin described as an input is received by the PHY. A basic description of each pin is provided. Signals named Lx_*, designate the per-lane signal where x = (0 to 3). For example, Lx_RX_P expands to the following signals L0_RX_P, L1_RX_P, L2_RX_P and L3_RX_P. All SSTL signaling is 2.5 V or 1.8 V selectable.
Table 4. Symbol L0_RX_P L0_RX_N L0_TX_P L0_TX_N L1_RX_P L1_RX_N L1_TX_P L1_TX_N L2_RX_P L2_RX_N L2_TX_P L2_TX_N L3_RX_P L3_RX_N L3_TX_P L3_TX_N
[1]
PCI Express serial data lines Pin D1 E1 F3 G3 G1 H1 J3 K3 K1 L1 M3 N3 N1 P1 T1 U1 Type input input output output input input output output input input output output input input output output Signaling PCIe I/O PCIe I/O PCIe I/O PCIe I/O PCIe I/O PCIe I/O PCIe I/O PCIe I/O PCIe I/O PCIe I/O PCIe I/O PCIe I/O PCIe I/O PCIe I/O PCIe I/O PCIe I/O Description lane 0 differential input receive pair with 50 on-chip termination[1] lane 0 differential output transmit pair with 50 on-chip termination[1] lane 1 differential input receive pair with 50 on-chip termination lane 1 differential output transmit pair with 50 on-chip termination lane 2 differential input receive pair with 50 on-chip termination lane 2 differential output transmit pair with 50 on-chip termination lane 3 differential input receive pair with 50 on-chip termination lane 3 differential output transmit pair with 50 on-chip termination
As PCIe specification defined.
Table 5. Symbol
PXPIPE interface transmit data signals Pin Type Signaling SSTL Description 8-bit transmit data input from the MAC to the PHY lane 0 selection input for the symbols of transmit data at lane 0; LOW = data byte; HIGH = control byte 8-bit transmit data input from the MAC to the PHY lane 1 selection input for the symbols of transmit data at lane 1; LOW = data byte; HIGH = control byte A9, B9, A10, input A11, B11, A12, B12, C12 C10 input
L0_TXDATA[7:0]
L0_TXDATAK
SSTL
L1_TXDATA[7:0]
G17, H17, input H16, J17, J16, K17, L16, L17 K15 input
SSTL
L1_TXDATAK
SSTL
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Objective data sheet
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PX1041A
PCI Express stand-alone X4 PHY
PXPIPE interface transmit data signals ...continued Pin U16, T15, U15, R14, T14, U13, T12, U12 R12 Type input Signaling SSTL Description 8-bit transmit data input from the MAC to the PHY lane 2
Table 5. Symbol
L2_TXDATA[7:0]
L2_TXDATAK
input
SSTL
selection input for the symbols of transmit data at lane 2; LOW = data byte; HIGH = control byte 8-bit transmit data input from the MAC to the PHY lane 3 selection input for the symbols of transmit data at lane 3; LOW = data byte; HIGH = control byte
L3_TXDATA[7:0]
U6, T6, U5, T5, U4, U3, T3, R3 R5
input
SSTL
L3_TXDATAK
input
SSTL
Table 6. Symbol
PXPIPE interface receive data signals Pin Type output Signaling SSTL Description 8-bit receive data output from the PHY lane 0 to the MAC selection output for the symbols of receive data at lane 0; LOW = data byte; HIGH = control byte 8-bit receive data output from the PHY lane 1 to the MAC
L0_RXDATA[7:0] A4, B5, A5, A6, B6, A7, B8, A8 L0_RXDATAK C4
output
SSTL
L1_RXDATA[7:0] A16, A17, B17, C17, D17, E17, F16, F17 L1_RXDATAK C16
output
SSTL
output
SSTL
selection output for the symbols of receive data at lane 1; LOW = data byte; HIGH = control byte 8-bit receive data output from the PHY lane 2 to the MAC
L2_RXDATA[7:0] M17, N17, P17, P16, R17, R16, T17, U17 L2_RXDATAK M16
output
SSTL
output
SSTL
selection output for the symbols of receive data at lane 2; LOW = data byte; HIGH = control byte 8-bit receive data output from the PHY lane 3 to the MAC selection output for the symbols of receive data at lane 3; LOW = data byte; HIGH = control byte
L3_RXDATA[7:0] U11, T11, U10, U9, T9, T8, U8, U7 L3_RXDATAK R10
output
SSTL
output
SSTL
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Objective data sheet
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PX1041A
PCI Express stand-alone X4 PHY
PXPIPE interface command signals Pin C11 L15 R13 R4 C9 Type input input input input input Signaling SSTL SSTL SSTL SSTL SSTL Description forces lane 0 TX output to electrical idle (see Table 13) forces lane 1 TX output to electrical idle (see Table 13) forces lane 2 TX output to electrical idle (see Table 13) forces lane 3 TX output to electrical idle (see Table 13) used when transmitting the compliance pattern at lane 0; HIGH-level sets the running disparity to negative used when transmitting the compliance pattern at lane 1; HIGH-level sets the running disparity to negative used when transmitting the compliance pattern at lane 2; HIGH-level sets the running disparity to negative used when transmitting the compliance pattern at lane 3; HIGH-level sets the running disparity to negative signals the PHY to perform a polarity inversion on the receive data at lane 0; LOW = PHY does no polarity inversion; HIGH = PHY does polarity inversion signals the PHY to perform a polarity inversion on the receive data at lane 1; LOW = PHY does no polarity inversion; HIGH = PHY does polarity inversion signals the PHY to perform a polarity inversion on the receive data at lane 2; LOW = PHY does no polarity inversion; HIGH = PHY does polarity inversion signals the PHY to perform a polarity inversion on the receive data at lane 3; LOW = PHY does no polarity inversion; HIGH = PHY does polarity inversion PHY reset input; active LOW instructs the PHY to begin a receiver detection operation or to begin loopback; LOW = reset state transceiver power-up and power-down inputs (see Table 12); 0x2 = reset state signals the PHY to start a lane to lane deskew (see Table 15); LOW = reset state signals the PHY to perform lane reversal (see Table 15), LOW = reset state
Table 7. Symbol
L0_TXIDLE L1_TXIDLE L2_TXIDLE L3_TXIDLE L0_TXCOMP
L1_TXCOMP
L14
input
SSTL
L2_TXCOMP
P13
input
SSTL
L3_TXCOMP
P4
input
SSTL
L0_RXPOL
C8
input
SSTL
L1_RXPOL
J15
input
SSTL
L2_RXPOL
N14
input
SSTL
L3_RXPOL
P5
input
SSTL
RESET_N RXDET_ LOOPB
A13 E15
input input
SSTL SSTL
PWRDWN0 PWRDWN1 DESKEW_ START LANEREVERS
C14 B14 B15 E14
input input input input
SSTL SSTL SSTL SSTL
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PX1041A
PCI Express stand-alone X4 PHY
PXPIPE interface command signals ...continued Pin C13 D13 D12 Type input input input Signaling SSTL SSTL SSTL Description signals the PHY to do loopback at PXPIPE side (see Table 15), LOW = reset state signals the PHY to switch from PXPIPE to PIPE interface, LOW = reset state enable the internal encoder to replace side-band signals to perform selected functions (see Table 15)
Table 7. Symbol
PIPELOOPB PIPESEL ENCODEN
Table 8. Symbol
PXPIPE interface status signals Pin C7 F14 M14 R6 D4 D16 M15 R11 C6 C5 D5 H15 G15 F15 R15 P15 N15 R7 R8 R9 C15 D15 Type output output output output output output output output output output output output output output output output output output output output output output Signaling SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL Description indicates symbol lock and valid data on RX_DATA and RX_DATAK at lane 0 indicates symbol lock and valid data on RX_DATA and RX_DATAK at lane 1 indicates symbol lock and valid data on RX_DATA and RX_DATAK at lane 2 indicates symbol lock and valid data on RX_DATA and RX_DATAK at lane 3 indicates receiver detection of an electrical idle at lane 0; this is an asynchronous signal indicates receiver detection of an electrical idle at lane 1; this is an asynchronous signal indicates receiver detection of an electrical idle at lane 2; this is an asynchronous signal indicates receiver detection of an electrical idle at lane 3; this is an asynchronous signal encodes receiver status and error codes for the received data stream and receiver detection at lane 0 (see Table 14) encodes receiver status and error codes for the received data stream and receiver detection at lane 1 (see Table 14) encodes receiver status and error codes for the received data stream and receiver detection at lane 2 (see Table 14) encodes receiver status and error codes for the received data stream and receiver detection at lane 3 (see Table 14) indicates the lane deskew is completed and passed (see Table 15) used to communicate completion of several PHY functions including power management state transitions and receiver detection
L0_RXVALID L1_RXVALID L2_RXVALID L3_RXVALID L0_RXIDLE L1_RXIDLE L2_RXIDLE L3_RXIDLE L0_RXSTATUS0 L0_RXSTATUS1 L0_RXSTATUS2 L1_RXSTATUS0 L1_RXSTATUS1 L1_RXSTATUS2 L2_RXSTATUS0 L2_RXSTATUS1 L2_RXSTATUS2 L3_RXSTATUS0 L3_RXSTATUS1 L3_RXSTATUS2 DESKEW_VALID PHYSTATUS
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Objective data sheet
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PX1041A
PCI Express stand-alone X4 PHY
Clock and reference signals Pin A15 Type input Signaling SSTL Description source synchronous 250 MHz transmit clock input from MAC. All input data and signals to the PHY are synchronized to this clock. source synchronous 250 MHz clock output for received data and status signals bound for the MAC. 100 MHz reference clock input. This is the spread spectrum source clock for PCI Express. Differential pair input with 50 on-chip termination. input or output to create a compensation signal internally that will adjust the I/O pads characteristics as PVT drifts. Connect to VDD through a 49.9 resistor. reference voltage input for SSTL signaling. Connect to 900 mV for SSTL_18, to 1.25 V for SSTL_2.
Table 9. Symbol TXCLK
RXCLK
A14
output
SSTL
REFCLK_P REFCLK_N
A1 B1
input input
PCIe I/O PCIe I/O
PVT
D3
-
analog I/O
VREFS
U14
input
Table 10. Symbol TMS TRST_N
3.3 V JTAG signals Pin A2 B2 Type input input Signaling 3.3 V CMOS 3.3 V CMOS Description test mode select input test reset input for the JTAG interface; active LOW. pull-down required for normal operation test clock input for the JTAG interface test data input test data output
TCK TDI TDO Table 11. Symbol VDDA1 VDDA2 VDDD1 VDDD2
B3 A3 C3
input input output
3.3 V CMOS 3.3 V CMOS 3.3 V CMOS
PCI Express PHY power supplies Pin J4, K4, L4, M4, N4 E4 C2 D7, D8, D10, D11, G14, H14, J14, K14, P10, P11, P12 Type power power power power Signaling Description 1.2 V analog power supply for serializer and de-serializer 3.3 V analog power supply for serializer and de-serializer 3.3 V power supply for JTAG I/O 2.5 V or 1.8 V power supply for SSTL I/O
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PX1041A
PCI Express stand-alone X4 PHY
PCI Express PHY power supplies ...continued Pin P7, P8 F4, G4, H4 Type power power Signaling Description 1.2 V power supply for core 1.2 V power supply for high-speed serial PCI Express I/O pads and PVT ground
Table 11. Symbol VDDD3 VDD VSS
B4, B7, B10, B13, B16, ground C1, D2, D6, D9, D14, E2, E3, E16, F1, F2, G2, G16, H2, H3, J1, J2, K2, K16, L2, L3, M1, M2, N2, N16, P2, P3, P6, P9, P14, R1, R2, T2, T4, T7, T10, T13, T16, U2
8. Functional description
The main function of the PHY is to convert digital data into electrical signals and vice versa. The PCI Express PHY handles the low level PCI Express protocol and signaling. The PX1041A PCI Express PHY consists of the Physical Coding Sub-layer (PCS), a Serializer and De-serializer (SerDes) and a set of I/Os (pads). The PCI Express PHY handles the low level PCI Express protocol and signaling. This includes features such as Clock and Data Recovery (CDR), data serialization and de-serialization, 8b/10b encoding, analog buffers, elastic buffer and receiver detection. The PXPIPE interface between the MAC and PX1041A is a superset of the PHY Interface for the PCI Express (PIPE) specification. The following feature have been added:
* Source synchronous clocks for RX and TX data to simplify timing closure.
The 4 x 8-bit data width PXPIPE interface operates at 250 MHz with SSTL Class I signaling at 2.5 V or 1.8 V. PX1041A does not integrate SSTL termination resistors inside the IC. Each PCI Express lane consists of a differential input pair and a differential output pair. The data rate per lane is 2.5 Gbit/s.
8.1 Receiving data
Incoming data enters the chip at the RX interface. The receiver converts these signals from small-amplitude differential signals into rail-to-rail digital signals. The carrier detect circuit detects whether data is present on the line and passes this information through to the SerDes and PCS. If a valid stream of data is present the Clock and Data Recovery unit (CDR) first recovers the clock from the data and then uses this clock for re-timing the data (i.e., recovering the data). The de-serializer or Serial-to-Parallel converter (S2P) de-serializes this data into 10-bits parallel data. Since the S2P has no knowledge about the data, the word alignment is still random. This is fixed in the digital domain by the PCS block. It first detects a 10-bit comma character (K28.5) from the random data stream and aligns the bits. Then it converts the 10-bit raw
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PCI Express stand-alone X4 PHY
data into 8-bit words using 8b/10b decoding. An elastic buffer and FIFO brings the resulting data to the right clock domain, which is the RX source synchronous clock domain.
8.2 Transmitting data
When the PHY transmits, it receives 4 x 8-bit data from the MAC. This data is encoded using an 8b/10b encoding algorithm. The 2 bits overhead of the 8b/10b encoding ensures the serial data will be DC-balanced and has a sufficient 0-to-1 and 1-to-0 transition density for clock recovery at the receiver side. The serializer or Parallel-to-Serial converter (P2S) serializes the 10 bits data into serial data streams. These data streams are latched into the transmitter, where they are converted into small amplitude differential signals. The transmitter has built-in de-emphasis for a larger eye opening at the receiver side. The PLL has a sufficiently high bandwidth to handle a 100 MHz reference clock with a 30 kHz to 33 kHz spread spectrum modulation.
8.3 Clocking
There are three clock signals used by the PX1041A:
* REFCLK is a 100 MHz external reference clock that the PHY uses to generate the
250 MHz data clock and the internal bit rate clock. This clock may have 30 kHz to 33 kHz Spread Spectrum Clock (SSC) modulation.
* TXCLK is a reference clock that the PHY uses to clock the TXDATA and command.
This source synchronous clock is provided by the MAC. The PHY expects that the rising edge of TXCLK is centered to the data. The TXCLK has to be the same frequency as RXCLK.
* RXCLK is a source synchronous clock provided by the PHY. The RXDATA and status
signals are synchronous to this clock. The PHY aligns the rising edge of RXCLK to the center of the data. RXCLK may be used by the MAC to clock its internal logic.
8.4 Reset
The PHY must be held in reset until power and REFCLK are stable. It takes the PHY 64 s maximum to stabilize its internal clocks. RXCLK frequency is the same as REFCLK frequency, 100 MHz, during this time. The PHY de-asserts PHYSTATUS when internal clocks are stable. The PIPE specification recommends that while RESET_N is asserted, the MAC should have RXDET_LOOPB de-asserted, TXIDLE asserted, TXCOMP de-asserted, RXPOL de-asserted and power state P1. The MAC can also assert a reset if it receives a physical layer reset packet.
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RXCLK
RESET_N
PHYSTATUS 100 MHz 250 MHz
002aac172
Fig 4. Reset
8.5 Power management
The power management signals allow the PHY to manage power consumption. The PHY meets all timing constraints provided in the PCI Express base specification regarding clock recovery and link training for the various power states. Four power states are defined: P0, P0s, P1 and P2. P0 state is the normal operational state for the PHY. When directed from P0 to a lower power state, the PHY can immediately take whatever power saving measures are appropriate. In states P0, P0s and P1, the PHY keeps internal clocks operational. For all state transitions between these three states, the PHY indicates successful transition into the designated power state by a single cycle assertion of PHYSTATUS. For all power state transitions, the MAC must not begin any operational sequences or further power state transitions until the PHY has indicated that the initial state transition is completed. TXIDLE should be asserted while in power states P0s and P1.
* P0 state: All internal clocks in the PHY are operational. P0 is the only state where the
PHY transmits and receives PCI Express signaling. P0 is the appropriate PHY power management state for most states in the Link Training and Status State Machine (LTSSM). Exceptions are listed for each lower power PHY state (P0s, P1 and P2).
* P0s state: The MAC will move the PHY to this state only when the transmit channel is
idle. While the PHY is in either P0 or P0s power states, if the receiver is detecting an electrical idle, the receiver portion of the PHY can take appropriate power saving measures. Note that the PHY is capable of obtaining bit and symbol lock within the PHY-specified time (N_FTS with or without common clock) upon resumption of signaling on the receive channel. This requirement only applies if the receiver had previously been bit and symbol locked while in P0 or P0s states.
* P1 state: Selected internal clocks in the PHY are turned off. The MAC will move the
PHY to this state only when both transmit and receive channels are idle. The PHY indicates a successful entry into P1 (by asserting PHYSTATUS). P1 should be used for the disabled state, all detect states, and L1.idle state of the Link Training and Status State Machine (LTSSM).
* P2 state: PHY will enter P2 and power down the TX and the RX PLLs. RXCLK is
turned off and the PHY interface is in asynchronous mode. The PHY still uses main power and cannot receive or transmit beacon.
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Table 12. 00b 01b 10b 11b
[1] [2]
Summary of power management state Power management state P0, normal operation P0s, power saving state P1, lower power state P2, lowest power state Transmitter on[1] idle[2] idle[2] idle[2] Receiver on idle idle idle TX PLL on on on off RXCLK on on on off RX PLL/CDR on on off off
PWRDWN[1:0]
TXIDLE = 0 TXIDLE = 1
8.6 Receiver detect
When the PHY is in the P1 state, it can be instructed to perform a receiver detection operation to determine if there is a receiver at the other end of the link. Basic operation of receiver detection is that the MAC requests the PHY to do a receiver detect sequence by asserting RXDET_LOOPB. When the PHY has completed the receiver detect sequence, each lane drives its own RXSTATUS signals to the value of 011b if a receiver is present, or to 000b if there is no receiver. Then the PHY will assert PHYSTATUS to indicate the completion of receiver detect operation. The MAC uses the rising edge of PHYSTATUS to sample each lane's RXSTATUS signals and then de-asserts RXDET_LOOPB. A few cycles after the RXDET_LOOPB de-asserts, the PHYSTATUS is also de-asserted.
TXCLK
RXDET_LOOPB PWRDWN1, PWRDWN0
10b
RXCLK
PHYSTATUS RXSTATUS2, RXSTATUS1, RXSTATUS0
000b
011b
000b
002aac173
Fig 5. Receiver detect - receiver present
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8.7 Loopback
The PHY supports an internal loopback from the PCI Express receiver to the transmitter of every lane with the following characteristics. The PHY retransmits each 10-bit data and control symbol exactly as received, without applying scrambling or descrambling or disparity corrections, with the following rules:
* If a received 10-bit symbol is determined to be an invalid 10-bit code (i.e., no legal
translation to a control or data value possible), the PHY still retransmits the symbol exactly as it was received.
* If a SKP ordered set retransmission requires adding a SKP symbol to accommodate
timing tolerance correction, any disparity can be chosen for the SKP symbol.
* The PHY continues to provide the received data on the PXPIPE interface, behaving
exactly like normal data reception.
* The PHY transitions from normal transmission of data from the PXPIPE interface to
looping back the received data at a symbol boundary. The PHY begins to loopback data when the MAC asserts RXDET_LOOPB while doing normal data transmission. The PHY stops transmitting data from the PXPIPE interface, and begins to loopback received symbols. While doing loopback, the PHY continues to present received data on the PXPIPE interface. The PHY stops looping back received data when the MAC de-asserts RXDET_LOOPB. Transmission of data on the parallel interface begins immediately. Since RXDET_LOOPB is a share signal, all lanes enter and exit the loopback mode at the same time. The timing diagram of Figure 6 shows example timing for beginning loopback. In this example, the receiver is receiving a repeating stream of bytes, Rx-a through Rx-z. Similarly, the MAC is causing the PHY to transmit a repeating stream of bytes Tx-a through Tx-z. When the MAC asserts RXDET_LOOPB to the PHY, the PHY begins to loopback the received data to the differential TX_P and TX_N lines.
TXCLK
RXDET_LOOPB
TXDATA[7:0]
Tx-m
Tx-n
Tx-o
Tx-p
Tx-q
RXCLK
RXDATA[7:0]
Rx-c
Rx-d
Rx-e
Rx-f
Rx-g
TX_P, TX_N
Tx-m
Tx-n
Rx-e
002aac174
Fig 6. Loopback start
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The timing diagram of Figure 7 shows an example of switching from loopback mode to normal mode. As soon as the MAC detects an electrical idle ordered-set, the MAC de-asserts RXDET_LOOPB, asserts TXIDLE and changes the POWERDOWN signals to state P1.
RXCLK
RXDATA[7:0]
COM
IDL
Junk
TXCLK
RXDET_LOOPB
TXIDLE includes electrical idle ordered set TX_P, TX_N Looped back RX data Junk
001aac785
Fig 7. Loopback end
8.8 Electrical idle and lane turn off
The PCI Express Base Specification requires that devices send an Electrical Idle ordered-set before TX goes to the electrical idle state. The timing diagram of Figure 8 shows an example of timing for entering electrical idle.
TXCLK
TXDATA[7:0]
ScZero
COM
IDL
TXDATAK
TXIDLE
TX_P, TX_N
active (ends with Electrical Idle ordered-set)
002aac175
Fig 8. Electrical idle
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Table 13 summarizes the function of some PXPIPE control signals.
Table 13. P0: 00b Control signals function summary RXDET_LOOPB 0 0 1 1 P0s: 01b P1: 10b X X 0 1 P2: 11b X TXIDLE 0 1 0 1 0 1 0 1 1 X Function description normal operation transmitter in idle loopback mode illegal illegal transmitter in idle illegal transmitter in idle receiver detect transmitter and receiver turned off. Remark: Beacon transmission and reception are not supported.
PWRDWN[1:0]
The MAC can disable one or more lanes which are not in use. The MAC asserts both Lx_TXIDLE and Lx_TXCOMP at the same time to instruct the PHY to turn off the corresponding lane x. The disabled lane(s) of the PHY will ignore all other signals from the MAC, except RESET_N. The MAC will ignore any signals from the disabled lane(s). When the MAC wants to turn on the disabled lane(s), it must reset the whole PHY as described in Section 8.4.
8.9 Clock tolerance compensation
The PHY receiver contains an elastic buffer used to compensate for differences in frequencies between bit rates at the two ends of a link. The elastic buffer is capable of holding at least seven symbols to handle worst case differences (600 ppm) in frequency and worst case intervals between SKP ordered-sets. The PHY is responsible for inserting or removing SKP symbols in the received data stream to avoid elastic buffer overflow or underflow. The PHY monitors the receive data stream, and when a Skip ordered-set is received, the PHY can add or remove one SKP symbol from each SKP ordered-set as appropriate to manage its elastic buffer. Whenever a SKP symbol is added or removed, the PHY will signal this to the MAC using the RXSTATUS signals. These signals have a non-zero value for one clock cycle and indicate whether a SKP symbol was added or removed from the received SKP ordered-set. RXSTATUS should be asserted during the clock cycle when the COM symbol of the SKP ordered-set is moved across the parallel interface. If the removal of a SKP symbol causes no SKP symbols to be transferred across the parallel interface, then RXSTATUS is asserted at the same time that the COM symbol (that was part of the received skip ordered-set) is transmitted across the parallel interface. Figure 9 shows a sequence where the PHY inserted a SKP symbol in the data stream. Figure 10 shows a sequence where the PHY removed a SKP symbol from a SKP ordered-set.
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RXCLK
RXDATA[7:0]
active
COM
SKP
SKP
active
RXVALID RXSTATUS2, RXSTATUS1, RXSTATUS0 000b 001b 000b
001aac779
Fig 9. Clock correction - insert a SKP
RXCLK
RXDATA[7:0]
active
COM
SKP
active
RXVALID RXSTATUS2, RXSTATUS1, RXSTATUS0 000b 010b 000b
002aac176
Fig 10. Clock correction - remove a SKP
8.10 Error detection
The PHY is capable of detecting receive errors of several types. These errors are signaled per lane to the MAC layer using the receiver status signals Lx_RXSTATUS.
Table 14. Function table PXPIPE status interface signals Output pin RXSTATUS2 RXSTATUS1 RXSTATUS0 Received data OK One SKP added One SKP removed Receiver detected 8b/10b decode error Elastic buffer overflow Elastic buffer underflow Receive disparity error L L L L H H H H L L H H L L H H L H L H L H L H
Operating mode
Because of higher level error detection mechanisms (like CRC) built into the data link layer of PCI Express, there is no need to specifically identify symbols with errors. However, timing information about when the error occurred in the data stream is important. When a receive error occurs, the appropriate error code is asserted for one clock cycle at the point closest to where the error actually occurred.
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There are four error conditions that can be encoded on the RXSTATUS signals. If more than one error should happen to occur on a received byte, the errors are signaled with the priority shown below. 1. 8b/10b decode error 2. Elastic buffer overflow 3. Elastic buffer underflow 4. Disparity error
8.10.1 8b/10b decode errors
For a detected 8b/10b decode error, the PHY places an EDB (EnD Bad) symbol in the data stream in place of the bad byte, and encodes RXSTATUS with a decode error during the clock cycle when the effected byte is transferred across the parallel interface. In Figure 11 the receiver is receiving a stream of bytes Rx-a through Rx-z, and byte Rx-c has an 8b/10b decode error. In place of that byte, the PHY places an EDB on the parallel interface, and sets RXSTATUS to the 8b/10b decode error code. Note that a byte that cannot be decoded may also have bad disparity, but the 8b/10b error has precedence.
RXCLK
RXDATA[7:0]
Rx-a
Rx-b
EDB
Rx-d
Rx-e
RXVALID RXSTATUS2, RXSTATUS1, RXSTATUS0 000b 100b 000b
001aac780
Fig 11. 8b/10b decode errors
8.10.2 Disparity errors
For a detected disparity error, the PHY asserts RXSTATUS with the disparity error code during the clock cycle when the effected byte is transferred across the parallel interface. In Figure 12 the receiver detected a disparity error on Rx-c data byte, and indicates this with the assertion of RXSTATUS.
RXCLK
RXDATA[7:0]
Rx-a
Rx-b
Rx-c
Rx-d
Rx-e
RXVALID RXSTATUS2, RXSTATUS1, RXSTATUS0 000b 111b 000b
001aac781
Fig 12. Disparity errors
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8.10.3 Elastic buffer
For elastic buffer errors, an underflow is signaled during the clock cycle when the spurious symbol is moved across the parallel interface. The symbol moved across the interface is the EDB symbol. In the timing diagram Figure 13, the PHY is receiving a repeating set of symbols Rx-a through Rx-z. The elastic buffer underflow causing the EDB symbol to be inserted between the Rx-c and Rx-d symbols. The PHY drives RXSTATUS to indicate buffer underflow during the clock cycle when the EDB is presented on the parallel interface.
RXCLK
RXDATA[7:0]
Rx-a
Rx-b
Rx-c
EDB
Rx-d
RXVALID RXSTATUS2, RXSTATUS1, RXSTATUS0 000b 110b 000b
001aac782
Fig 13. Elastic buffer underflow
For an elastic buffer overflow, the overflow is signaled during the clock cycle where the dropped symbol would have appeared in the data stream. In the timing diagram of Figure 14, the PHY is receiving a repeating set of symbols Rx-a through Rx-z. The elastic buffer overflows causing the symbol Rx-d to be discarded. The PHY drives RXSTATUS to indicate buffer overflow during the clock cycle when Rx-d would have appeared on the parallel interface.
RXCLK
RXDATA[7:0]
Rx-a
Rx-b
Rx-c
Rx-e
Rx-f
RXVALID RXSTATUS2, RXSTATUS1, RXSTATUS0 000b 101b 000b
001aac783
Fig 14. Elastic buffer overflow
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8.11 Polarity inversion
The PHY supports lane polarity inversion for each lane. The PHY inverts received data for the lane which has its corresponding Lx_RXPOL asserted. The PHY begins data inversion within 20 symbols after RXPOL is asserted.
RXCLK
RXDATA[7:0]
D21.5
D21.5
D10.2
D10.2
RXVALID
RXPOL
001aac786
Fig 15. Polarity inversion
8.12 Setting negative disparity
To set the running disparity to negative, the MAC asserts the corresponding Lx_TXCOMP for one clock cycle that matches with the data that is to be transmitted with negative disparity.
TXCLK
TXDATA[7:0]
data
K28.5
K28.5
K28.5
K28.5
TXCOMP byte transmitted with negative disparity TX_P, TX_N valid data K28.5- K28.5+
002aac177
Fig 16. Setting negative disparity
8.13 JTAG boundary scan interface
Joint Test Action Group (JTAG) or IEEE 1149.1 is a standard, specifying how to control and monitor the pins of compliant devices on a printed-circuit board. This standard is commonly known as `JTAG Boundary Scan'. This standard defines a 5-pin serial protocol for accessing and controlling the signal levels on the pins of a digital circuit, and has some extensions for testing the internal circuitry on the chip itself, which is beyond the scope of this data sheet. Access to the JTAG interface is provided to the customer for the sole purpose of using boundary scan for interconnect test verification between other compliant devices that may reside on the board. Using JTAG for purposes other than boundary scan may produce undesired effects.
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The JTAG interface is a 3.3 V CMOS signaling. JTAG TRST_N must be asserted LOW for normal device operation. If JTAG is not planned to be used, it is recommended to pull down TRST_N and other JTAG input signals to VSS via resistors.
8.14 Optional functions
The PHY supports some optional functions:
* * * *
Lane-to-lane deskew Lane reversal PXPIPE-side parallel loopback PIPE mode select
These features can be activated by either the side-band signals or the in-band encoded commands. When ENCODEN pin is set to LOW, all functions will be controlled by the dedicated side-band signal pins; When ENCODEN pin is set to HIGH, the PHY expects encoded commands to activate the required function. Any activity on the corresponding pins will be ignored. Table 15 summarizes these optional functions.
Table 15. Optional functions summary ENCODEN = 0 1 = start lane-to-lane deskew 1 = indicates deskew operation is completed and passed 1 = causes all lanes to reverse 0 = PXPIPE interface selected 1 = PIPE interface selected PIPELOOPB 1 = at PXPIPE side, TXDATA[7:0] directly loopback to RXDATA[7:0] ENCODEN = 1 don't care; PHY expects an encoded command don't care; PHY expects an encoded command don't care; PHY expects an encoded command 0 = PXPIPE interface selected 1 = PIPE interface selected 0 = PHY expects an encoded command 1 = reserved
Side-band signals DESKEW_START DESKEW_VALID LANEREVERS PIPESEL
The principle of the in-band signaling is based on the use of some invalid 8b/10b special character symbols as encoded commands. Table 16 summarizes the encoded commands, and Table 17 is for the status signals.
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Table 16. Command function Plain COMMA
Encoded commands Encoded TXDATA[7:0], TXDATAK TXDATA7 TXDATA6 TXDATA5 TXDATA4 TXDATA3 TXDATA2 TXDATA1 TXDATA0 TXDATAK 1 0 0 1 1 1 1 1 1 1 1 0 0 0 1 1 1
COMMA with 1 lane-to-lane deskew COMMA with 1 lane reversal COMMA with 1 lane reversal and lane-to-lane deskew start 0 PXPIPE-side loopback stop 0 PXPIPE-side loopback Table 17. Command function
0 0
1 1
1 1
1 1
1 1
1 1
0 1
1 1
0
1
0
0
0
1
0
1
0
0
0
0
0
1
0
1
Encoded status Encoded RXDATA[7:0], RXDATAK RXDATA7 RXDATA6 RXDATA5 RXDATA4 RXDATA3 RXDATA2 RXDATA1 RXDATA0 RXDATAK 0 0 1 1 1 1 1 1
lane-to-lane 1 deskew completed and passed lane-to-lane 1 deskew completed but failed performing 1 lane-to-lane deskew
0
0
1
1
1
1
0
1
0
0
1
1
1
0
1
1
The PHY has priority to choose the physical lane 0 as the master lane, unless the lane has been turned off. The encoded commands and status signals should go to L0_TXDATA and L0_RXDATA, and affect all four lanes. If lane 0 is turned off, then the next highest physical lane becomes the master lane.
8.14.1 Lane-to-lane deskew
Lane-to-lane deskewing is required by PCIe specification, and is typically implemented in the MAC. When the PHY offers the feature of receiver lane-to-lane deskew, the MAC needs to instruct the PHY to start the lane deskew function when it is needed. The PHY will respond with some status signals. With the side-band signal, the PHY will detect the rising edge of the DESKEW_START to start the deskew operation. The PHY responds back by asserting DESKEW_VALID for a single cycle if deskew is completed and passed. The MAC needs a built-in counter to
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check for the assertion of DESKEW_VALID signal, and if the MAC does not see this signal go valid within the 32 RXCLK cycles time-out period, it considers the deskew failed and can reinstruct the PHY to perform deskew by deasserting and reasserting DESKEW_START. Using in-band signals, the MAC send encoded lane-to-lane deskew command to PHY, and the PHY will respond with encoded status signal. if deskewing is successful, the MAC then send the PHY the special COMMA with bit 0 = 0, shown at Table 16, to stop the deskew. If deskewing fails, the MAC should first stop the deskew, then may resend the encoded deskew start command to restart the deskew process. The PHY internally arbitrates to decide the master lane to use for deskewing. All lanes that are turned off by the MAC, do not take part in arbitration or deskewing. The PHY has priority to choose lane 0 as the master lane, unless the lane has been turned off. Even when lane reversal is enabled and physical lane 0 becomes logical lane 3, physical lane 0 still has priority for becoming the master. When the PHY is configured to perform lane-to-lane deskew the information about SKP insertion and removal from the PHY should be ignored by the MAC. This is because the deskewing is done by the PHY and hence the skip insertion and removal information is not required. All other information like decode error, disparity error, FIFO overflow, FIFO underflow, and OK are valid.
8.14.2 Lane reversal
Lane reversal for multi-lane implementation is particularly useful to ease PCB layout. It swaps the physical lane0, lane1, lane2, and lane3 to the logical lane3, lane2, lane1, and lane0, respectively. This feature is typically performed in the MAC. PX1041A has this optional built-in feature. It is required to have a signal from the MAC to the PHY to enable it. When the MAC asserts LANEREVERS, the PHY will enable the feature. Alternatively, the MAC can send the encoded command listed in Table 16 to enable this feature.
8.14.3 PXPIPE-side parallel loopback
The function of PXPIPE-side parallel loopback is mainly for test debugging purposes to check the PCB connection between the MAC and the PHY. The PHY will loopback any data that is present on the Lx_TXDATA and Lx_TXDATAK lines to the corresponding Lx_RXDATA and Lx_RXDATAK. PIPELOOPB being HIGH will enable the feature, or the MAC may use the encoded commands in Table 16. This feature requires the PHY to be in the P1 state.
8.14.4 PIPE Mode
By default, the interface between the MAC and PX1041A is PXPIPE, which has source synchronous clocks for transmit and receive data. The PIPE mode, which uses a single clock, RXCLK, for both transmit and receive, is selectable by setting the PIPESEL pin HIGH.
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9. Limiting values
Table 18. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VDDD1 VDDD2 VDDD3 VDD VDDA1 VDDA2 Vesd Tstg Tj Tamb Parameter digital supply voltage 1 digital supply voltage 2 digital supply voltage 3 supply voltage analog supply voltage 1 analog supply voltage 2 electrostatic discharge voltage storage temperature junction temperature ambient temperature operating commercial industrial
[1] [2] [3] No select pin needed. Human Body Model: ANSI/EOS/ESD-S5.1-1994, standard for ESD sensitivity testing, Human Body Model Component level; Electrostatic Discharge Association, Rome, NY, USA. Charged Device Model: ANSI/EOS/ESD-S5.3.1-1999, standard for ESD sensitivity testing, Charged Device Model - component level; Electrostatic Discharge Association, Rome, NY, USA.
Conditions for JTAG I/O for SSTL I/O for core for high-speed serial I/O and PVT for serializer for serializer HBM CDM
[2] [3] [1] [1]
Min -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -55 -55 0 -40
Max +4.6 +3.75 +1.7 +1.7 +1.7 +4.6 2000 500 +150 +125 +70 +85
Unit V V V V V V V V C C C C
10. Thermal characteristics
Table 19. Symbol Rth(j-a) Thermal characteristics Parameter thermal resistance from junction to ambient Conditions in free air, JEDEC test card in free air, JEDEC test card
[1]
Typ 32.6
Unit K/W
Rth(j-c)
thermal resistance from junction to case
[1]
6.9
K/W
[1]
Significant variations can be expected due to system variables, such as adjacent devices, or actual air flow across the package.
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11. Characteristics
Table 20. Symbol Supplies VDDD1 VDDD2 VDDD2 VDDD3 VDD VDDA1 VDDA2 IDDD1 IDDD2 IDDD3 IDD IDDA1 IDDA2 Reference clock fclk(ref) fmod(clk)(ref) fmod(clk)(ref) VIH(se)REFCLK VIL(se)REFCLK Receiver UI VRX_DIFFp-p tRX_MAX_JITTER VIDLE_DET_DIFFp-p ZRX_DC ZRX_HIGH_IMP_DC RLRX_DIFF RLRX_CM tlock(CDR)(ref) tlock(CDR)(data) tRX_latency LRX_SKEW
PX1041A_1
PCI Express PHY characteristics Parameter digital supply voltage 1 digital supply voltage 2 digital supply voltage 2 digital supply voltage 3 supply voltage analog supply voltage 1 analog supply voltage 2 digital supply current 1 digital supply current 2 digital supply current 3 supply current analog supply current 1 analog supply current 2 reference clock frequency reference clock SSC modulation frequency deviation reference clock SSC modulation frequency REFCLK single-end HIGH-level input voltage REFCLK single-end LOW-level input voltage unit interval differential input peak-to-peak voltage maximum receiver jitter time electrical idle detect threshold DC input impedance powered-down DC input impedance differential return loss common mode return loss CDR lock time (reference loop) CDR lock time (data loop) receiver latency total skew 1 clock cycle is 4 ns Conditions for JTAG I/O for SSTL_18 I/O for SSTL_2 I/O for core for high-speed serial I/O and PVT for serializer for serializer for JTAG I/O for SSTL I/O; no load for core for high-speed serial I/O and PVT for serializer for serializer Min 3.0 1.7 2.3 1.15 1.15 1.15 3.0 99.97 -0.5 30 Typ 3.3 1.8 2.5 1.2 1.2 1.2 3.3 100 0.7 0 Max 3.6 1.9 2.7 1.25 1.25 1.25 3.6 2 80 60 100 100 60 Unit V V V V V V V mA mA mA mA mA mA
100.03 MHz +0 33 % kHz V V
399.88 400 0.175 65 40 200 10 6 50 -
400.12 ps 1.2 0.6 175 60 20 V UI mV k dB dB s s clock cycle ns
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Table 20. Symbol
PCI Express PHY characteristics ...continued Parameter unit interval differential peak-to-peak output voltage maximum time between the jitter median and maximum deviation from the median maximum transmitter jitter time de-emphasized differential output voltage ratio D+/D- TX output rise time D+/D- TX output fall time RMS AC peak common mode output voltage Conditions Min Typ Max Unit
Transmitter UI VTX_DIFFp-p tTX_EYE_m-mJITTER tTX_JITTER_MAX VTX_DE_RATIO tTX_RISE tTX_FALL VTX_CM_ACp 399.88 400 0.8 -3.0 50 50 0 0 0 10 6 40 75 1 clock cycle is 4 ns -3.5 50 100 400.12 ps 1.2 50 100 -4.0 20 100 25 3.6 90 60 200 50 64 500 + 2UI V ps ps dB ps ps mV mV mV V mA dB dB nF s clock cycle s s s ps
VCM_DC_ACT_IDLE absolute delta of DC common mode voltage during L0 and electrical idle VCM_DC_LINE VTX_CM_DC ITX_SHORT RLTX_DIFF RLTX_CM ZTX_DC CTX tlock(PLL) tTX_latency tP0s_exit_latency tP1_exit_latency tRESET-PHYSTATUS LTX_SKEW absolute delta of DC common mode voltage between D+ and D- TX DC common mode voltage TX short-circuit current limit differential return loss common mode return loss transmitter DC impedance AC coupling capacitor PLL lock time transmitter latency P0s state exit latency P1 state exit latency RESET_N HIGH to PHYSTATUS LOW time lane-to-lane output skew
PX1041A_1
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Objective data sheet
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PCI Express stand-alone X4 PHY
Table 21. Symbol fRXCLK fTXCLK VVREFS VVREFS VOH(SSTL18) VOL(SSTL18) VIH(SSTL18) VIL(SSTL18) VOH(SSTL2) VOL(SSTL2) VIH(SSTL2) VIL(SSTL2)
PXPIPE characteristics Parameter RXCLK frequency TXCLK frequency voltage on pin VREFS voltage on pin VREFS SSTL_18 HIGH-level output voltage SSTL_18 LOW-level output voltage SSTL_18 HIGH-level AC input voltage SSTL_18 LOW-level AC input voltage SSTL_2 HIGH-level output voltage SSTL_2 LOW-level output voltage SSTL_2 HIGH-level AC input voltage SSTL_2 LOW-level AC input voltage for SSTL_18 for SSTL_2 VTT = 900 mV VTT = 900 mV Vref = 900 mV Vref = 900 mV VTT = 1.25 V VTT = 1.25 V Vref = 1.25 V Vref = 1.25 V see Figure 17 see Figure 17 see Figure 17 see Figure 17
[1] [1]
Conditions
Min 249.925 249.925 1.50 1.15 1.85 1.56 500 500 1500 1500
Typ 250 250 900 1.25 -
Max 250.075 250.075 0.30 0.65 0.64 0.94 -
Unit MHz MHz mV V V V V V V V V V ps ps ps ps
Input signals; measured with respect to TXCLK tsu(TX)(PXPIPE) setup time of PXPIPE input signal th(TX)(PXPIPE) hold time of PXPIPE input signal Output signals; measured with respect to RXCLK tsu(RX)(PXPIPE) setup time of PXPIPE output signal th(RX)(PXPIPE)
[1]
hold time of PXPIPE output signal
Reference voltage for SSTL I/O.
TXCLK
PXPIPE INPUT t su(TX)(PXPIPE) t h(TX)(PXPIPE)
RXCLK
PXPIPE OUTPUT t su(RX)(PXPIPE) t h(RX)(PXPIPE)
002aac316
Fig 17. Definition of PXPIPE timing
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Objective data sheet
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NXP Semiconductors
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PCI Express stand-alone X4 PHY
12. Package outline
LFBGA208: plastic low profile fine-pitch ball grid array package; 208 balls; body 15 x 15 x 1 mm SOT631-4
D
B
A
ball A1 index area
E A
A2 A1
detail X
e1 e b v w
M M
CAB C
C y1 C y
U T R P N M L K J H G F E D C B A
e e2
ball A1 index area
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17
X
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max 1.5 A1 0.4 0.3 A2 1.10 0.95 b 0.5 0.4 D 15.1 14.9 E 15.1 14.9 e 0.8 e1 12.8 e2 12.8 v 0.15 w 0.08 y 0.12 y1 0.1
OUTLINE VERSION SOT631-4
REFERENCES IEC JEDEC MO-205 JEITA
EUROPEAN PROJECTION
ISSUE DATE 07-03-09 07-03-19
Fig 18. Package outline SOT631-4 (LFBGA208)
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Objective data sheet
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PX1041A
PCI Express stand-alone X4 PHY
13. Soldering
This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 "Surface mount reflow soldering description".
13.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization.
13.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following:
* Through-hole components * Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are:
* * * * * *
Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus PbSn soldering
13.3 Wave soldering
Key characteristics in wave soldering are:
* Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are exposed to the wave
* Solder bath specifications, including temperature and impurities
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PCI Express stand-alone X4 PHY
13.4 Reflow soldering
Key characteristics in reflow soldering are:
* Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 19) than a PbSn process, thus reducing the process window
* Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
* Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 22 and 23
Table 22. SnPb eutectic process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 2.5 2.5 Table 23. 235 220 Lead-free process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 1.6 1.6 to 2.5 > 2.5 260 260 250 350 to 2000 260 250 245 > 2000 260 245 245 350 220 220
Package thickness (mm)
Package thickness (mm)
Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 19.
PX1041A_1
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Objective data sheet
Rev. 01 -- 21 June 2007
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NXP Semiconductors
PX1041A
PCI Express stand-alone X4 PHY
temperature
maximum peak temperature = MSL limit, damage level
minimum peak temperature = minimum soldering temperature
peak temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 19. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365 "Surface mount reflow soldering description".
14. Abbreviations
Table 24. Acronym BER BIST CMOS EMI ESD FPGA LTSSM MAC P2S PCI PCS PHY PLL PIPE PVT RX S2P SerDes SKP
PX1041A_1
Abbreviations Description Bit Error Rate Built-In Self Test Complementary Metal Oxide Semiconductor ElectroMagnetic Interference ElectroStatic Discharge Field Programmable Gate Array Link Training and Status State Machine Media Access Control Parallel to Serial Peripheral Component Interconnect Physical Coding Sub-layer PHYsical layer Phase-Locked Loop PHY Interface for the PCI Express Process Voltage Temperature Receive Serial to Parallel Serializer and De-serializer SKiP
(c) NXP B.V. 2007. All rights reserved.
Objective data sheet
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NXP Semiconductors
PX1041A
PCI Express stand-alone X4 PHY
Abbreviations ...continued Description Spread Spectrum Clock modulation Stub Series Terminated Logic for 1.8 Volts Stub Series Terminated Logic for 2.5 Volts Transmit
Table 24. Acronym SSC SSTL_18 SSTL_2 TX
15. References
[1] [2] PCI Express Base Specification -- Rev. 1.1 - PCISIG PHY Interface for the PCI Express Architecture Version 2.00 -- Intel Corporation
16. Revision history
Table 25. Revision history Release date 20070621 Data sheet status Objective data sheet Change notice Supersedes Document ID PX1041A_1
PX1041A_1
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Objective data sheet
Rev. 01 -- 21 June 2007
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PCI Express stand-alone X4 PHY
17. Legal information
17.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
17.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.
17.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or
17.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.
18. Contact information
For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: salesaddresses@nxp.com
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Objective data sheet
Rev. 01 -- 21 June 2007
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PX1041A
PCI Express stand-alone X4 PHY
19. Contents
1 2 2.1 2.2 2.3 2.4 2.5 2.6 3 4 5 6 7 7.1 7.2 8 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 8.10 8.10.1 8.10.2 8.10.3 8.11 8.12 8.13 8.14 8.14.1 8.14.2 8.14.3 8.14.4 9 10 11 12 13 13.1 13.2 13.3 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 PCI Express interface . . . . . . . . . . . . . . . . . . . . 1 PHY/MAC interface. . . . . . . . . . . . . . . . . . . . . . 1 JTAG interface . . . . . . . . . . . . . . . . . . . . . . . . . 2 Power management . . . . . . . . . . . . . . . . . . . . . 2 Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7 Functional description . . . . . . . . . . . . . . . . . . 12 Receiving data . . . . . . . . . . . . . . . . . . . . . . . . 12 Transmitting data . . . . . . . . . . . . . . . . . . . . . . 13 Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Power management . . . . . . . . . . . . . . . . . . . . 14 Receiver detect. . . . . . . . . . . . . . . . . . . . . . . . 15 Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Electrical idle and lane turn off . . . . . . . . . . . . 17 Clock tolerance compensation . . . . . . . . . . . . 18 Error detection . . . . . . . . . . . . . . . . . . . . . . . . 19 8b/10b decode errors . . . . . . . . . . . . . . . . . . . 20 Disparity errors . . . . . . . . . . . . . . . . . . . . . . . . 20 Elastic buffer . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Polarity inversion. . . . . . . . . . . . . . . . . . . . . . . 22 Setting negative disparity . . . . . . . . . . . . . . . . 22 JTAG boundary scan interface . . . . . . . . . . . . 22 Optional functions . . . . . . . . . . . . . . . . . . . . . . 23 Lane-to-lane deskew . . . . . . . . . . . . . . . . . . . 24 Lane reversal . . . . . . . . . . . . . . . . . . . . . . . . . 25 PXPIPE-side parallel loopback . . . . . . . . . . . . 25 PIPE Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 26 Thermal characteristics. . . . . . . . . . . . . . . . . . 26 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 27 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 30 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Introduction to soldering . . . . . . . . . . . . . . . . . 31 Wave and reflow soldering . . . . . . . . . . . . . . . 31 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 31 13.4 14 15 16 17 17.1 17.2 17.3 17.4 18 19 Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 33 34 34 35 35 35 35 35 35 36
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2007.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 21 June 2007 Document identifier: PX1041A_1

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